Typically, a computer system contains a microprocessor, a bus, and other peripheral devices. The microprocessor executes logical operations on the data in the computer system. The bus is utilized by the microprocessor and peripheral devices to transfer data, address and control signals. The peripheral devices are either storage devices, input/output (I/O) devices, etc. Generally, everything in the computer system operates at the same frequency (i.e. cycle type).
The microprocessor has a core unit for processing the data. The core consists of the central processing unit (CPU), the cache memory, etc. The microprocessor communicates with the bus using a bus controller. Since all operations of the computer system occur at the same frequency, the logic operations performed by the core are at the same frequency as the transfer of data, address and control signals on the computer system bus. The bus controller ensures this timing by generating the control signals for the bus.
Some logic operations performed by the core unit, such as arithmetic operations, require multiple cycles to complete. During completion of these multiple cycle operations, the bus remains idle. The present invention allows the core unit to operate at a faster speed than the bus. By doing this, the bus is used to transfer data more frequently. Therefore, bus idle states are minimized and operations can be performed more quickly.
When changing the microprocessor to operate at a faster rate, it is advantageous to modify it in such a way as to minimize changes to the rest of the computer system. In this way, the new microprocessor need only be inserted into the computer system without changing any of the other system hardware (i.e., without totally redesigning the board). It is also advantageous to keep hardware changes to a minimum so that preexisting computer applications can benefit by upgrading their computer systems without having to acquire new system components, thereby avoiding huge expenditures.
To facilitate these requirements, the present invention provides a microprocessor which can be operated at both the bus speed and at a speed faster than the bus speed. The present invention allows the timing specifications of the bus to remain the same in either mode. In this way, changes to the entire computer system are minimized.
The advantage of the present invention over the prior art is that it permits a microprocessor design to be modified to allow the core to operate at a multiple of the bus frequency with only a very small number of design changes. This drastically reduces design time. Moreover, using this technique, the majority of the bus control logic (approximately 99%) can be designed assuming operation at the bus speed only. This approach also allows the addition of select logic to permit a single bond pad to select between the fast and slow modes of operation. This single die design can therefore be used to fulfill the requirements of a number of microprocessor types through the use of wire bond programming of the select logic pad.